module counter(
    input wire clk,
    input wire reset,
    input wire horl,
    output wire[31:0] time1
    );
    reg [63:0]count;
    always@(posedge clk)begin
        if(reset)count <= 0;
        else count <= count + 1;
    end
    assign time1 = horl ? count[63:32] : count[31:0]; 
endmodule